1. Field of the Invention
The present invention relates to a manufacturing method of a junction gate field effect transistor formed on an insulating substrate, and more particularly to a manufacturing method in which fine working or processing utilizing a focused ion beam technique is effected to form a junction gate field effect transistor of high performance in a simple process(es).
2. Description of the Background Art
As a background of the invention, an operation of a conventional junction gate field effect transistor (will be also call as "JFET" herein) will be described below with reference to FIGS. 1A-1C.
A JFET shown in FIGS. 1A-1C is formed on a so-called bulk silicon substrate, and the operation thereof can be described as follows (e.g., according to "Physics and Technology of Semiconductor Devices" A. S. Grove, p 244). In the conventional JFET shown in FIG. 1A, a substrate 1 and a region 2a below a gate electrode 2 are p-type regions having a high concentration, and a channel region 3 is a n-type region having a low concentration. As shown in FIG. 1A, when the gate electrode 2, a substrate electrode 4 and a source electrode 5 are grounded and a voltage V.sub.D at a drain electrode 6 is of a low value near 0 (zero), narrow depletion layers 7a and 7b are spread between the region 2a and the channel region 3 and between the p-type region of the substrate 1 and the channel region 3, respectively. In this condition, a path for a drain current I.sub.D flowing between the source electrode 5 and the drain electrode 6 is formed at a center of the channel region 3 located below the gate electrode 2. When the drain voltage V.sub.D is increased from this condition, the depletion layers 7a and 7b spread at the proximity of the drain electrode 6, narrowing a width of the channel region 3 in this area, which increases a resistance between the source electrode 5 and the drain electrode 6. When the drain voltage V.sub.D increases to a predetermined value V.sub.DSAT, the depletion layers 7a and 7b connect to each other, and thus the channel region is divided (FIG. 1B). When the drain voltage V.sub.D increases over V.sub.DSAT, overlapping portions of the depletion layers 7a and 7b further increases (FIG. 1C), but the drain current I.sub.D increases no longer and tends to exhibit a saturation state.
If a negative voltage is applied to the gate electrode 2 and the substrate electrode 4, the depletion layers 7a and 7b spread to a larger extent with the same V.sub.D. Utilizing this, potentials in the gate electrode 2 and the substrate electrode 4 may be changed to control the drain current I.sub.D. The drain voltage V.sub.D and the drain current I.sub.D have a relationship as shown by a graph in FIG. 1D.
Then, a structure and a manufacturing method of a conventional JFET which is formed on a SOI (Silicon on Insulator) including an insulating substrate and a monocrystal silicon layer grown thereon. The conventional SOI type JFET shown in FIG. 2A and 2B has a channel region 11 electrically floated by an insulating substrate 12. As shown in FIG. 2B, a gate electrode 14 made from doped polysilicon is buried in a center of the channel region 11, so that a current in the channel region 11 may be controlled by the gate electrode 14 even if a monocrystal silicon layer 11 formed on the insulating substrate 12 has a large thickness. On applying a predetermined voltage to the gate electrode 14, a depletion layer 15 spreads as shown in FIG. 2A and 2B, and thus narrows a path 11a for the current in the channel region 11, so that the resistance in this region increases. In this manner, a drain current flowing between a source region 16 and a drain region 17 can be controlled. The monocrystal silicon layer 13 is covered with a silicon oxide film 18, and a surface of the gate electrode 14 is covered with a silicon oxide film 19. On the silicon oxide film 19, there are provided wiring layers 22 and 23 of, e.g., aluminum, connected to the source region 16 and the drain region 17 through contact holes 20 and 21, respectively. As the SOI techniques for forming the monocrystal silicon layer 13 on the insulating substrate 12, there are following techniques: a gas phase growth method in which epitaxial growth of silicon is effected on crystalline insulating material having a lattice constant nearly equal to that of the silicon; a solid phase growth method in which a silicon substrate is covered with SiO.sub.2 except for a portion forming an opening, an amorphous silicon film is then deposited thereon and an annealing is effected for a long time at an temperature of about 600.degree. C. to perform a solid phase epitaxial growth; a melting crystallization method in which polycrystal silicon layer deposited on an insulating layer is partially heated e.g., by a laser beam to form a molten region and recrystallization is effected while moving the molten region on a wafer; and an insulating film burying method in which oxygen or nitrogen ions are implanted at about 10.sup.18 dose into a monocrystal silicon, leaving the monocrystal silicon on the surface and forming a SiO.sub.2 layer or a S.sub.3 N.sub.4 layer at the interior (For example, "Applied Physics", Vol. 54, NO. 12, 1985, pp. 1274-1283). As a typical SOI substrate formed by the gas phase growth method, there is a SOS (Silicon-on-sapphire) including a sapphire substrate and a monocrystal silicon film grown thereon. Among the SOI techniques utilizing the insulating film burying method, a technique utilizing implantation of oxygen ions is called as SIMOX (Separation by Implanted Oxygen). A laminated substrate, in which a substrate and a monocrystal silicon layer are stuck together with an insulating film therebetween.
The conventional manufacturing method of the SOI type JFET described above will be further described below with reference to FIG. 3A-3J.
FIG. 3A illustrates a sectional structure of a SOI substrate at a start of the manufacturing of the SOI type JFET. The SOI substrate includes an insulating substrate 12 and a monocrystal silicon layer 13 grown thereon by any method described above. A resist film 24 is initially formed only on an region forming JFET in a surface of the monocrystal silicon layer 13 in the SOI substrate, and then patterning of the monocrystal silicon layer 13 is effected by etching to form structure shown in FIG. 3B. Before or after this patterning, implantation of impurity ions is effected for setting a resistance value in a region which will become a channel region in the JFET. In the following description, it is assumed that a conductivity type of the channel is a p-type and arsenic ions are implanted at about 1.times.10.sup.12 dose into the whole active region.
After separation of the active area by the patterning of the monocrystal silicon layer 13 described above and removal of the resist layer 24, a silicon oxide film 18 of about 2000 .ANG. is deposited on the whole surface of the wafer by the CVD method (FIG. 3C).
Then, a resist film 25 is formed on the silicon oxide film 18, and the monocrystal sillicon layer 13 and the silicon oxide film 18 are partially removed to form a portion 26 for burying a gate electrode, using a lithography technique and etching (FIG. 3D). Then, polysilicon 27 in which impurity ions are doped is deposited on the whole surface of the wafer for forming the gate electrode (FIG. 3E). Alternately, undoped polysilicon may be deposited, and PSG (Phosphosilicate Glass) may be formed on the surface thereof to diffuse phosphorus (P) contained in the PSG into the polysilicon.
A resist film 28 is then formed, and patterning for the gate electrode 14 is effected by the lithography. Before removing the resist film 28, phosphorus or arsenic is implanted at 1.times.10.sup.15 dose into the whole surface of the wafer to form a source region 16 and a drain region 17 by self-alignment (FIG. 3F).
After removing the resist film 28, a silicon oxide film 19 of about 2000 .ANG. in thickness is deposited as a layer insulating film (FIG. 3G), and after forming the resist film 29, the contact holes 20 and 21 are formed by the lithography and the etching (FIG. 3H).
After removing the resist film 29, a metal layer 30 is deposited on the whole surface of the wafer, and a pattern of the resist film 31 is formed for patterning the metal layer 30 by the lithography (FIG. 3I). Then, the patterning is effected by the etching to form the wiring layers 22 and 23, whereby the wiring in the transistor is completed (FIG. 3J).
However, the conventional method described above, in which the JFET is formed on the SOI substrate, has following problems.
In the above conventional manufacturing steps, the lithography technique employing reduction projection with the light is utilized in the step for applying and patterning the resist film. In this photolithography technique, as shown in FIG. 4, the light in a predetermined pattern passed through the mask 31 is projected by a reduction optical system 32 on a resist film 35 applied on the polysilicon layer 34 and the silicon oxide film 33 for the exposure. In FIG. 4, minimum values of pattern sizes indicated by S and L are limited to a value of 0.4-0.5 .mu.m which is similar to the wave length of the light.
On the other hand, the width of the depletion layer formed between the gate and the channel is determined by the concentration of the impurities in the channel, and a width W.sub.D of the depletion layer and a reverse bias voltage V.sub.R applied across the gate electrode and the drain electrode have a relationship as indicated by a graph in FIG. 5 with respect to various impurity concentrations C.sub.B. For example, at the impurity concentration C.sub.B of 1.times.10.sup.15 cm.sup.-3, the width W.sub.D of the depletion layer is nearly more than 1 .mu.m, and thus the channel part can be fully depleted even if the gate electrode is formed with a conventional minimum processing size. In this case, the electrical resistance is however increased at the channel part, and thus a high drain current can not be flowed. In order to reduce the electrical resistance at the channel part, it is necessary to increase the channel concentration. For example, at the channel concentration of 1.times.10.sup.17 cm.sup.-3, the electrical resistance can be reduced by two orders. However, by applying the reverse bias voltage V.sub.R in such a case, the depletion layer spreading in the channel region have the width W.sub.D of the about 0.1 .mu.m. Therefore, in the processing technique utilizing the conventional lithography technique, it is difficult to form the channel of sizes enough to fully deplete the channel region in this channel concentration.
The foregoing can be summarized in general as follows with respect to SOI type JFET.
Referring to FIG. 6, a SOI type JFET 52 including implanted gate electrodes 51, which are n in number, in the channel is required to satisfy a following conditional expression for effectively operating the gate electrode to control the drain current with a p-n junction; EQU n D.sub.G +2 n W.sub.D &gt;W.sub.C
where D.sub.G is a diameter of the buried gate electrode, W.sub.D is a spread width of the depletion layer 53, and W.sub.C is a channel width.